CRU firmware compilation error

O² O² CRU
1

I followed the instructions of the git repository

git clone https://gitlab.cern.ch/alice-cru/pcoresng-cru.git
cd pcoresng-cru/preint/syn-cru-v2
make ip_gen; make synthesis

but the compilation fails with some errors like

Warning: spage_monitoring: Component type spage_monitoring is not in the library
Error: pciemmdma_ext_custom_spage_monitoring.spage_monitoring: Component spage_monitoring 1.0 not found or could not be instantiated
Warning: pciemmdma_ext_custom_spage_monitoring.interface_requirements: Your system is missing the required interface "clock". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: pciemmdma_ext_custom_spage_monitoring.interface_requirements: Your system is missing the required interface "monitoring". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: pciemmdma_ext_custom_spage_monitoring.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
Warning: pciemmdma_ext_custom_spage_monitoring.interface_requirements: Your system is missing the required interface "spage_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
Error: qsys-generate failed with exit code 1: 1 Error, 5 Warnings
...
Error: Missing required switch --spd

For the bookkeeping, here are also the other errors, shown by the build (each one appears multiple times):

Error: pciemmdma_ext_custom_reset_ctrl.reset_ctrl: Component reset_ctrl 1.2 not found or could not be instantiated
Error: pciemmdma_ext_custom_dmafifo_bar_controller.dmafifo_bar_controller: Component dmafifo_bar_controller 1.1 not found or could not be instantiated
Error: pciemmdma_ext_custom_descriptor_controller_monitoring.descriptor_controller_monitoring: Component descriptor_controller_monitoring 1.0 not found or could not be instantiated
Error: pciemmdma_ext_custom_dbg_reg.dbg_reg: Component dbg_reg 1.3 not found or could not be instantiated
Error: pciemmdma_ext_custom_data_flow_controller.data_flow_controller: Component data_flow_controller 1.6 not found or could not be instantiated
Error: pciemmdma_ext_custom_data_emulator_controller.data_emulator_controller: Component data_emulator_controller 2.0 not found or could not be instantiated
Error: pciemmdma_ext_custom_bar_latency.bar_latency: Component bar_latency 1.0 not found or could not be instantiated

I’m using Quarts 17.0.2 Pro to compile and I also changed my quartus2.ini according to the git.

2

Ciao Sebastian,
indeed we are looking into that.
Could you try to compile again removing the content of the file quartus2.ini

I had similar issue and after removing the settings in the file I managed to compile QSYS without problems.
I don’t know what is affecting it … I will check with the other colleague.

Cheers
PiPPo

3

Thanks, I will try.

Just guessing: it could be because the variables

HDL_PREFERENCE = Verilog
MANAGED_FLOW_HDL_PREFERENCE = Verilog

were set to Verilog. We saw already in the past that this could cause compilation errors.
(I will try after I managed to compile it without any settings in the quartus2.ini)

1 Like
4

Indeed it could be.
Ill check with the other colleague and see … apparently we get different compilation report on different machines/environment.

5

Hi,

i was compiling it on our build server and on my local machine. I did not set the two variables and it compiled fine for me.

1 Like
6

Hello,

For me the ip_gen worked with a fresh copy (and the compilation started without errors too).

My quartus2.ini is

[General 17.0_pro]
pro_allow_all_back_annotation = on

[Programmer 17.0_pro]
PGMDQ_INTERNAL_SETTING = 0
PGMW_SFL_USE_CRC_CHECK = on

Cheers,
Tuan

7

Ok,
we did a fast round of check.
Apparently the error is the option with Verilog as value.

We will update the README accordingly.
Thx you all for the feedback

8

ok, great that you found the issue!

But how does this get together with the statement in /preint/README.md

To simulate the design, first use quartus to generate all simulation models (in verilog, the VHDL models contains syntax errors, true in 17.0) and the combined simulation script.

So if I want to simulate something, I have to change my quartus2.ini to generate the IP cores in Verilog (with the correct simulation model) but If I want to compile the design, I have to change it back to VHDL?

9

Ciao,
I don’t think so … let me check with Olivier, he is our simulation expert.

10

Hello,

No tweaks in the ini are needed, indeed the IP generation scripts indicate in its command options which language to use:

qsys-generate $i --synthesis=VERILOG --simulation=VERILOG --family=“Arria 10” --part=$FPGA_PART --clear-output-directory

So you should be all set.

11

Ok, thank you very much for the clarification.