Debug info from GBT_FPGA core

In ITS we have been chasing data corruption on the GBT link and were able to debug a lot of it due to the debug capabilities included in the GBT_FPGA core as provided by the GBT group. One specific item that we used a lot was a counter that counts the number of FEC corrected words and another that shows the bits that were changed due to the FEC. Another item that we built into our CRU emulator was the capability to send patterns in t he payload to send to the FEE and then a pattern checker that compares the returned payload.
We would now like to test the same things with the “real” CRU rather than our CRU emulator to see if some of the issues we see are due to our hardware only. So are any of these debug capabilities available in the latest CRU firmware?


Yes most of these exist in the CRU firmware and the associated support software :

  • the FEC counter is implemented and limited to 16 bit (see cru.gbt.fecstat()). But this is all encapsulated in the script)
  • The bit changed are not provided
  • the pattern sending and checking is also available (fixed and counter), again please check what is called in

Best regards